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AS6C62256A-70SIN SRAM Asynchronous Memory IC 256Kbit Parallel 70 ns 28-SOP Electronic IC Chip

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AS6C62256A-70SIN SRAM Asynchronous Memory IC 256Kbit Parallel 70 ns 28-SOP Electronic IC Chip

Name: AS6C62256A70SIN SRAM Asynchronous Memory IC 256Kbit Parallel 70 ns 28SOP Electronic IC Chip
Brand: Alliance Memory, Inc.
Price: 1 USD

China AS6C62256A-70SIN SRAM Asynchronous Memory IC 256Kbit Parallel 70 ns 28-SOP Electronic IC Chip wholesale

Brand Name : Alliance Memory, Inc.

Model Number : AS6C62256A-70SIN

Certification : ISO9001

MOQ : >=1pcs

Price : request for need

Payment Terms : L/C, T/T, D/A, D/P, Western Union,

Supply Ability : 100000 Acre/Acres per Day+pcs+1-2days

Delivery Time : 2-3days

Packaging Details : Tape & Reel (TR) Cut Tape (CT) Digi-Reel

Place of Origin : China

Description : IC SRAM 256KBIT PARALLEL 28SOP

Mounting Type : Surface Mount

Operating Temperature : -40°C ~ 85°C

Package / Case : 28-SOIC

Voltage - Supply : 4.5V ~ 5.5V

Memory Size : 256Kbit

Technology : SRAM - Asynchronous

Product Status : Active

Base Product Number : W971GG8

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AS6C62256A-70SIN SRAM Asynchronous Memory IC 256Kbit Parallel 70 ns 28-SOP Electronic IC Chip

PRODUCT DESCRIPTION

Part number AS6C62256A-70SIN is manufactured by Alliance Memory, Inc and distributed by Stjk. As one of the leading distributors of electronic products, we carry many electronic components from the world's top manufacturers.

For more information on AS6C62256A-70SIN detailed specifications, quotations, lead times, payment terms and more, please do not hesitate to contact us. In order to process your enquiry, please add the quantity AS6C62256A-70SIN to your message. Send an email to stjkelec@hotmail.com for a quote now.

The AS6C62256A is a static RAM manufactured using a CMOS process technology with the following operating modes: - Read - Standby - Write - Data Retention The memory array is based on a 6- transistor cell.

The circuit is activated by the falling edge of E. The address and control inputs open simultaneously. According to the information of W and G, the data inputs, or outputs, are active. In a Read cycle, the data outputs are activated by the falling edge of G, afterwards the data word read will be available at the outputs DQ0-DQ7. After the address change, the data outputs go High-Z until the new information read is available.

The data outputs have not preferred state. The Read cycle is finished by the falling edge of W, or by the rising edge of E, respectively.

Data retention is guaranteed down to 2 V. With the exception of E, all inputs consist of NOR gates, so that no pull-up/pull-down resistors are required.

AS6C62256A-70SIN SRAM Asynchronous Memory IC 256Kbit Parallel 70 ns 28-SOP Electronic IC Chip

AS6C62256A-70SIN SRAM Asynchronous Memory IC 256Kbit Parallel 70 ns 28-SOP Electronic IC Chip Images

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